Clock Cycle and Throughput:
Clock Period(T)=max{ti}1k+d=Tm+d; Ti: Time Delay of the circuitry in stage Si.
d: The time delay of latches.
Pipeline frequency is defined as the inverse of the clock period:
f=1/T;
If one results if expected to come out of the pipeline per cycle, f represent the Maximum throughput of the pipeline.
Clock Skewing:
It is expected that the clock pulse will arrive to all stages at same time but due to a problem known as clock skewing, the same clock pulse may arrive at different stages with a time offset of s.
Speedup Factor:
The speedup factor of a k-stage pipeline over a non-pipelined processor is defined as:
Sk=T1/Tk=nkT/(kT+(n-1)T)
=nk/(k+(n-1))
Efficiency and Throughput:
Efficiency of a k-stage linear pipeline Ek=(Sk/k)=n/(k+(n-1))
The Pipeline Throughput Hk is defined as the number of task performed per unit time.
Hk=nf/(k+(n-1))
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