Asynchronous Model
Synchronous Model
Data flow between adjacent stages is controlled by handshaking protocol.
Clocked latches are used to interface between stages.
Different amount of delay may be experienced in different stages.
Approximately equal amount of delay is    experienced in all stages.
Ready and Acknowledgement signals are used for communication purpose.
No such signals are used for communication purpose.
Transfer of data to various stages in not simultaneous.
All Latches Transfer of data to next stage simultaneous.
No Concept of Combinational Circuit is used in pipeline stages.
Pipeline stages are combinational logic circuits.