Asynchronous Model
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Synchronous Model
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Data flow between adjacent stages is controlled by handshaking protocol.
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Clocked latches are used to interface between stages.
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Different amount of delay may be experienced in different stages.
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Ready and Acknowledgement signals are used for communication purpose.
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No such signals are used for communication purpose.
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Transfer of data to various stages in not simultaneous.
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All Latches Transfer of data to next stage simultaneous.
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No Concept of Combinational Circuit is used in pipeline stages.
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Pipeline stages are combinational logic circuits.
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